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CONFIDENTIAL
[AK4201]
= Preliminary =
AK4201
Stereo Cap-less HP-Amp
GENERAL DESCRIPTION The AK4201 is an audio stereo cap-less headphone amplifier. The AK4201 eliminates the need for large DC-blocking capacitors with a built-in Charge-pump circuit. The PSRR (Power supply Rejection Ratio) can achieve to 100dB with a built-in regulator, and it can output 2Vrms with excellent linearity when used as lineout amplifier. The AK4201 is available in tiny 12-pin USON (2.2 X 2.9mm), saving board space, cost, and component height. FEATURE Stereo Cap-less Amplifier (No DC-blocking capacitors required) High PSRR (100dB at 217Hz) Output Power: 65 mW x 2ch @ 16, AVDD=PVDD=5.0V, THD+N=-40dB 30 mW x 2ch @ 16, AVDD=PVDD=3.3V, THD+N=-40dB Output Noise Level: 11Vrms (Ri=20k, Rf=30k) Line-Out level: 2.0Vrms @ 5k, AVDD=PVDD=5.0V 2.0Vrms @ 5k, AVDD=PVDD=3.3V Regulator built-in THD+N: -60 dB @ 16, 50mW, AVDD=PVDD=5.0V -60 dB @ 16, 20mW, AVDD=PVDD=3.3V -90 dB @ 5k, 2Vrms, AVDD=PVDD=5.0V -90 dB @ 5k, 2Vrms, AVDD=PVDD=3.3V Low Power Shutdown Mode 0.1A (typ) Adjustable Gain Range: -16 dB ~ 16dB Pop noise free at power-ON/OFF Power Supply: 2.6V ~ 3.6V or 4.5V ~ 5.5V Ta: -40 85C Package: 12pin USON (2.2 x 2.9mm, 0.5mm pitch)
Rev 0.2 -1-
2008/07
CONFIDENTIAL
[AK4201]
Block Diagram
Rf
AVDD
Regulator
Ci
Ri
LIN
Amp
LOUT
VSS2
AK4201
Regulator
ROUT
Ci
Ri
RIN
Amp
PVDD
Charge Pump
PDN
VSS1 CP
CN
PVEE
Rf
Figure 1. AK4201 Block Diagram
Rev 0.2 -2-
2008/07
CONFIDENTIAL
[AK4201]
Ordering Guide
AK4201EU AKD4201 -40 +85C 12pin USON (2.2mm x 2.9mm, 0.5mm pitch) Evaluation board for AK4201
Pin Layout
LIN
1
12
RIN
LOUT
2
11
ROUT
AVDD
3
Top View
10
PVEE
VSS1
4
9
VSS2
PVDD
5
8
PDN
CN
6
7
CP
Rev 0.2 -3-
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CONFIDENTIAL
[AK4201]
PIN/FUNCTION
No. 1 2 3 4 5 6 7 8 Pin Name LIN LOUT AVDD VSS1 PVDD CN CP PDN I/O I O O O I Function L-channel analog input L-channel analog output Headphone positive power supply pin, 2.6V ~ 5.5V Power ground Charge-pump positive power supply pin, 2.6V ~ 5.5V Negative charge-pump capacitor terminal pin Positive charge-pump capacitor terminal pin Power-down mode pin "H": Power-up, "L": Power-down Signal ground; connect to VSS1 Charge-pump circuit negative voltage output pin R-channel analog output R-channel analog input
9 VSS2 10 PVEE O 11 ROUT O 12 RIN I Note. PDN pin should not be floated.
Handling of Unused Pin
The unused I/O pins should be processed appropriately as below. Classification Analog Pin Name LIN, RIN, LOUT, ROUT Setting Connect Output pin to Input pin when one channel is used and the other is not used. (Example) Connect the LOUT pin to the LIN pin if Lch is not used.
Rev 0.2 -4-
2008/07
CONFIDENTIAL
[AK4201]
ABSOLUTE MAXIMUM RATING (VSS1=VSS2 =0V (Note 1)) Parameter Symbol min Power Supplies: Analog AVDD -0.3 (Note 2) Charge Pump PVDD -0.3 Input Current, Any Pin Except Supplies IIN Input Voltage (Note 3) VIN -0.3 Ambient Temperature (powered applied) Ta -40 Storage Temperature Tstg -65 Maximum Power Dissipation (Note 4) Pd -
max 6.0 6.0 10 (AVDD + 0.3) or 6.0 85 150 TBD
Units V V mA V C C W
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMEND OPERATING CONDITIONS (VSS1=VSS2 =0V (Note 1)) Parameter Symbol min Analog 4.5 AVDD, PVDD Power Charge Pump 2.6 Supplies (Note 5) Difference -0.3 AVDD - PVDD
Parameter External Input Resistance External Feedback Resistance Load Resistance (LOUT, ROUT pins) Capacitance (LOUT, ROUT pins) Capacitance (LIN, RIN pins) Symbol Ri Rf RL CL Csum min 10 10 16 -
typ 5.0 3.3 0 typ -
max 5.5 3.6 0.3 max 100 100 300 20
Units V V Units k k pF pF
Note 1. All voltages are respect to ground. Note 2. VSS1 and VSS2 must be connected to the same analog plane. Note 3. LIN, RIN, PDN pin The maximum value is low value either (AVDD+0.3) V or 6.0V. Note 4. 2ch Output Power (Po, when load is 16) should be less TBD W. Note 5. The power up sequence among AVDD, PVDD is not critical. The PDN pin should be held to "L" when powered-up. The PDN pin should be set to "H" after all power supplies are powered-up. The PDN pin should be held to "L", when powered-down. Operation by the power-supply voltage from 3.6 to 4.5V is prohibited.
Note: AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet.
Rev 0.2 -5-
2008/07
CONFIDENTIAL
[AK4201]
ANALOG CHARACTERISTICS (AVDD=PVDD=5.0V) (AVDD=PVDD=5.0V; PDN=5.0V; Ta=25C; VSS1=VSS2=0V; Input Signal Frequency =1kHz; Measurement band width=10Hz 20kHz; Gain=+3.5dB (Ri=20k, Rf=30k); Headphone-Amp: RL =16; Charge Pump Circuit External Capacitance: C1=C2= 1F (Figure 3), unless otherwise specified) Parameter min typ max Units Output Power 65 mW RL =16, 0.68Vrms Input THD+N TBD dB -40 0.68Vrms Input; Po = 65mW @ RL =16 TBD dB -60 0.60Vrms Input; Po = 50mW @ RL =16 TBD dB 1.33Vrms Input; Vo = 2.0Vrms @ RL =5k -90 S/N (Signal-to-Noise Ratio) TBD 102 dB RL =16 (A-weighted) (Note 6) TBD 108 dB RL =5k (A-weighted) (Note 7) PSRR (Power Supply Rejection Ratio) (Note 8) 217Hz 100 dB 1kHz 90 dB Interchannel Isolation 60 80 dB RL =16 80 dB RL =5k 0.5 5.0 mV Output Offset Voltage 50 ms Start-up time (Note 9) Power Supplies 4 TBD mA AVDD + PVDD (Normal Mode; No Output) 0.1 TBD uA AVDD + PVDD (Power-Down Mode, PDN =0V)
Note 6. In case of 0.68Vrms Input (Po=65mW). Note 7. In case of 1.33Vrms Input (Vo=2Vrms). Note 8. PSR is applied to AVDD and PVDD with 500mVpp sine wave. Note 9. The time from PDN pin= "H" to when the AK4201 can output the data.
Rev 0.2 -6-
2008/07
CONFIDENTIAL
[AK4201]
ANALOG CHARACTERISTICS (AVDD=PVDD=3.3V) (AVDD=PVDD=3.3V; PDN=3.3V; Ta=25C; VSS1=VSS2=0V; Input Signal Frequency =1kHz; Measurement band width=10Hz 20kHz; Gain=+3.5dB (Ri=20k, Rf=30k); Headphone-Amp: RL =16; Charge Pump Circuit External Capacitance: C1=C2= 1F (Figure 3), unless otherwise specified) Parameter min typ max Units Output Power 30 mW RL =16, 0.46Vrms Input THD+N -40 TBD dB 0.46Vrms Input; Po = 30mW @ RL =16 -60 TBD dB 0.27Vrms Input; Po = 10mW @ RL =16 -90 TBD dB 1.33Vrms Input; Vo = 2.0Vrms @ RL =5k S/N (Signal-to-Noise Ratio) 92 98 dB RL =16 (A-weighted) (Note 10) 100 106 dB RL =5k (A-weighted) (Note 11) PSRR (Power Supply Rejection Ratio) (Note 12) 217Hz 70 dB 1kHz 70 dB Interchannel Isolation 60 80 dB RL =16 80 dB RL =5k mV Output Offset Voltage 0.5 5.0 50 ms Start-up time (Note 13) Power Supplies 4 TBD mA AVDD + PVDD (Normal Mode; No Output) 0.1 TBD AVDD + PVDD (Power-Down Mode, PDN =0V) A
Note 10. In case of 0.46Vrms Input (Po=30mW). Note 11. In case of 1.33Vrms Input (Vo=2Vrms). Note 12. PSR is applied to AVDD and PVDD with 100mVpp sine wave. Note 13. The time from PDN pin= "H" to when the AK4201 can output the data.
Rev 0.2 -7-
2008/07
CONFIDENTIAL
[AK4201]
DC & SWITCHING CHARACTERISTICS (Ta= -40 85C; AVDD=PVDD=2.6 3.6V or 4.5 5.5V, Note 14) Parameter Symbol min High-Level Input Voltage VIH 1.5 Low-Level Input Voltage VIL Input Leakage Current Iin Power-down (PDN pulse Width) tPD 150 Note 14. Apply to the PDN pin.
typ -
max 0.5 2 -
Units V V A ns
Timing Diagram
tPD VIH VIL
PDN
Figure 2. Power-down Timing
Rev 0.2 -8-
2008/07
CONFIDENTIAL
[AK4201]
OPERATION OVERVIEW
Charge Pump Circuit
The charge pump operates by the output of a regulator which uses PVDD voltage. The negative power supply (PVEE) for headphone amplifiers is generated from internal charge pump circuit. The external capacitors are showed in Figure 3. Low ESR (Equivalent Series Resistance) capacitors (more than -35% difference including temperature characteristics and piece to piece variations) are recommended for C1 and C2.
Headphone-amp negative voltage PVEE pin C1: 1uF CN pin Charge Pump Circuit C2: 1uF CP pin VSS1
Figure 3. Charge Pump Circuit External Capacitor
Headphone-Amp (LOUT/ROUT pins)
Power supply voltage for headphone amplifiers is supplied by a regulator for positive power and a charge-pump for negative power. The positive power supply for Charge pump is generated from the output of a regulator which is driven by PVDD. The headphone amplifier output is single-ended and centered on VSS1(0V). Therefore, a capacitor for AC-coupling can be removed. The minimum load resistance is 16. The output impedance is 20 (typ) when powered-down.
Rev 0.2 -9-
2008/07
CONFIDENTIAL
[AK4201]
Power-Up/Down Sequence
The PDN pin must keep "L" until all power supply pins (AVDD, PVDD) are supplied, and must be set to "H" after all powers are supplied.
Power Supply (1) Former Device DAC etc
Don't Care
Power Up (No Signal Output)
Normal Operation
Don't Care
Ta (2) Former Device Click noise 0V A
(4)
PDN pin 0V PVEE pin (3) PVEE pin Output =-3.3V(Typ.) (5) 0V
HPL/HPR pins
0V
Normal Operation(0V Common)
0V
Figure 4. Power-up/down Sequence example (1) The interval from power Up to PDN pin = "L" "H" "L" time of 150ns or more is needed to reset the AK4201. The power should be ON in state of the PDN pin = "L". The PDN pin should be set to "H" after power supply (AVDD, PVDD) are ON. (2) The interval from former device of the AK4201(DAC etc) power up to the PDN pin = "L" "H" The former device of the AK4201 should be powered up with no output (MUTE). When step wave which generated by former device is output (an instant change of DC offset), HPF response wave will occur at "A" period of the Figure 4, according to the AK4201 input coupling condenser (Ci) and input resistor (Ri). In order to avoid click noise, "Ta" wait time is needed after former device output. Ta calculation example: (in the case of Ci =0.22uF, Ri = 20k) =0.22u * 20k = 4.4ms Ta =* 7.6 = 33ms (When noise level by former device= 2V, response wave level= 1mV. 7.6* is needed) If waiting time is not sufficient, click noise maybe occur, but no problem for later working. (3) 50ms (max.) later, after the PDN pin went to "H", the AK4201 will be in normal operation mode and click noise is decreased. In this interval (50ms), the former device should be MUTE. (4) The former device should starts outputting the signal after the AK4201 starts Normal Operation. If click noise is generated by former device when MUTE is canceled, it will be output from the AK4201. (5) The PDN pin = "L". LOUT/ROUT pins short to VSS1 with 20(typ.). After 50ms (max.), the PVEE pin will be 0V according to a capacitor which connected to PVEE and internal resistance (typ. 17.5k). The AK4201 can be powered up again after 150ns or more from the PDN = "L".
Rev 0.2 - 10 -
2008/07
CONFIDENTIAL
[AK4201]
SYSTEM DESIGN
Ci Analog Input 0.22
Ri
Top View
1 LIN
RIN 12
Rf Rf 30k 30k
Ri 20k
Ci 0.22 Analog Input
20k
2 LOUT 3 AVDD
+ 10 10 + 0.1
ROUT 11 PVEE 10 1 VSS2 9 PDN 8 CP 7 (+)
Power Supply 4.55.5V, 2.63.6V
4 VSS1
0.1
Power Supply 4.55.5V, 2.63.6V
5 PVDD 6 CN
DSP or P
1
(+)
Note: 1. The PDN pin should be held to "L" when powered-up. The PDN pin should be set to "H" after all power supplies are powered-up. When power-down the AK4201, the PDN pin should be held to "L".
Refer to "Power-Up/Down Sequence" to avoid pop noise when power-up/down the AK4201. 1) Power-Up The power should be ON when the PDN pin = "L". The PDN pin should be set to "H" 150ns after all power supplies (AVDD, PVDD) are ON. 150ns "L" time or more is needed to reset the AK4201. 2) Power-Down The AK4201 should be powered-down when the PDN pin = "L". 2. 1uF~2.2uF ceramic capacitors (35% including temperature characteristics and piece-to-piece variations)should be connected to between the Cp and Cn pins, and the VSS1 and PVEE1 pins. 3. Both lines from the LIN pin and RIN pin to each Input resistance Ri and feedback resistance Rf should be short as possible. 4. A capacitor should be connected to the each LIN and RIN pin for AC coupling.
Rev 0.2 - 11 -
2008/07
CONFIDENTIAL
[AK4201]
PACKAGE
12pin USON (2.2mm x 2.9mm, 0.5mm pitch)
= Preliminary =
2.9 0.05
2.9 0.05 0.5 0.225 0.05 0.175 0.05 0.05
2.2 0.05
2.2 0.05
0.08 0.05
0.25 0.05
1.35 0.05
2.6 0.05
M
Rev 0.2 - 12 -
0.6MAX
2008/07
CONFIDENTIAL
[AK4201]
MARKING
4201
XXXX
1
XXXX: Date code (4 digit)
IMPORTANT NOTICE These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification.
Rev 0.2 - 13 -
2008/07

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